On maximal intermediate predicate constructive logics

We extend to the predicate frame a previous characterization of the maximal intermediate propositional constructive logics. This provides a technique to get maximal intermediate predicate constructive logics starting from suitable sets of classically valid predicate formulae we call maximal nonstandard predicate constructive logics. As an example of this technique, we exhibit two maximal intermediate predicate constructive logics, yet leaving open the problem of stating whether the two logics are distinct. Further properties of these logics will be also investigated.Presented by H. Ono     

Contrary-to-duty obligations

We investigate under what conditions contrary-to-duty (CTD) structures lacking temporal and action elements can be given a coherent reading. We argue, contrary to some recent proposals, that CTD is not an instance of defeasible reasoning, and that methods of nonmonotonic logics are inadequate since they are unable to distinguish between defeasibility and violation of primary obligations. We propose a semantic framework based on the idea that primary and CTD obligations are obligations of different kinds: a CTD obligation pertains to, or pre-supposes, a certain context in which a primary obligation is already violated. This framework is presented initially as an extension of Standard Deontic Logic (SDL), a normal modal logic of type KD, and is illustrated by application to a series of examples. The concluding section is concerned with some resemblances between CTD and defeasible reasoning. We show first that the SDL-based framework contains a flaw and must be adjusted. A discussion of possible adjustments, including an alternative treatment in terms of a preference-based semantics, reveals difficulties that are reminiscent of problems in defeasible reasoning and intensional accounts of defeasible conditionals.     

Quantum MV algebras

We introduce the notion of quantum MV algebra (QMV algebra) as a generalization of MV algebras and we show that the class of all effects of any Hilbert space gives rise to an example of such a structure. We investigate some properties of QMV algebras and we prove that QMV algebras represent non-idempotent extensions of orthomodular lattices.I should like to thank Prof. M.L. Dalla Chiara and Dr. P. Minari for many interesting comments and remarks. Daniele Mundici     

Prima facie obligation

This paper presents a nonmonotonic deontic logic based on commonsense entailment. It establishes criteria a successful account of obligation should satisfy, and develops a theory that satisfies them. The theory includes two conditional notions of prima facie obligation. One is constitutive; the other is epistemic, and follows nonmonotonically from the constitutive notion. The paper defines unconditional notions of prima facie obligation in terms of the conditional notions.     

Detachment and defeasibility in deontic logic

The purpose of the paper is to present a logical framework that allow to formalize a kind of prima facie duties, defeasible conditional duties, indefeasible conditional duties and actual (indefeasible) duties, as well as to show their logical interconnections.     

由三个宽恕模型看宽恕研究新进展

西方学者已普遍接受宽恕的本质即为亲社会性动机转变过程。从这一取向出发, 介绍Worthington提出的宽恕压力应对模型、Koutsos等人提出的人际间相关变量模型以及Hall和Fincham提出的自我宽恕模型这三个模型。三个模型从三个不同角度对宽恕的动机转变观点提供支持, 通过论述三个模型之间的关系, 对宽恕的动机转变观点进行更加深入的阐述。同时在宽恕模型论述中总结分析近年来宽恕的认知加工、人际相关变量的作用以及自我宽恕方面的研究进展等。最后对宽恕在西方以及我国的研究进行回顾, 指出中西方宽恕研究发展中存在的研究不全面、缺乏理论支持等问题。     

A multiple-valued logic approach to the design and verification of hardware circuits

We present a novel approach, which is based on multiple-valued logic (MVL), to the verification and analysis of digital hardware designs, which extends the common ternary or quaternary approaches for simulations. The simulations which are performed in the more informative MVL setting reveal details which are either invisible or harder to detect through binary or ternary simulations. In equivalence verification, detecting different behavior under MVL simulations may lead to the discovery of a genuine binary non-equivalence or to a qualitative gap between two designs. The value of a variable in a simulation may hold information about its degree of truth and its “place of birth” and “date of birth”. Applications include equivalence verification, initialization, assertions generation and verification, partial control on the flow of data by prioritizing and block-oriented simulations. Much of the paper is devoted to theoretical aspects behind the MVL approach, including the reason for choosing a specific algebra for computations and the introduction of the notions of De Morgan Canonical Form and of verification complexity of Boolean expressions. Two basic simulation-based algorithms are presented, one for satisfying and verifying combinational designs and the other for equivalence verification of sequential designs.     

Bunched sequential information

It is known that the logic BI of bunched implications is a logic of resources. Many studies have reported on the applications of BI to computer science. In this paper, an extension BIS of BI by adding a sequence modal operator is introduced and studied in order to formalize more fine-grained resource-sensitive reasoning. By the sequence modal operator of BIS, we can appropriately express “sequential information” in resource-sensitive reasoning. A Gentzen-type sequent calculus SBIS for BIS is introduced, and the cut-elimination and decidability theorems for SBIS are proved. An extension of the Grothendieck topological semantics for BI is introduced for BIS, and the completeness theorem with respect to this semantics is proved. The cut-elimination, decidability and completeness theorems for SBIS and BIS are proved using some theorems for embedding BIS into BI.     

Formal assessment of reliability specifications in embedded cyber-physical systems

Reliability has become an integral component of the design intent of embedded cyber-physical systems. Safety-critical embedded systems are designed with specific reliability targets, and design practices include the appropriate allocation of both spatial and temporal redundancies in the implementation to meet such requirements. With increasing complexity of such systems and considering the large number of components in such systems, redundancy allocation requires a formal scientific basis. In this work, we profess the analysis of the redundancy requirement upfront with the objective of making it an integral part of the specification. The underlying problem is one of synthesizing a formal specification with built-in redundancy artifacts, from the formal properties of the error-free system, the error probabilities of the control components, and the reliability target. We believe that upfront formal analysis of redundancy requirements is important in budgeting the resource requirements from a cost versus reliability perspective. Several case-studies from the automotive domain highlight the efficacy of our proposal.